`include "FETCH.v"
module TB_MEM;

reg clk = 0;
reg [31:0] addr;
reg enable;

wire [3:0] icode;
wire [3:0] ifun;
wire [3:0] rA;
wire [3:0] rB;
wire [31:0] valC;
wire [31:0] valP;
wire WAIT;

wire [15:0] mem_data;

wire [31:0] mem_addr;

always @(valP) begin
	addr <= valP;
end

assign mem_data = mem_addr[15:0];

always #1 clk <= !clk;






//////////////// BUS//////////////

BUS b(.MEM_ADDR,
      .MEM_DATA,
      .WE_N,
      .OE_N,
      .UB_N,
      .LB_N,
      .CE_N,
      .INIT_ADDR,
      .INIT_DATA_IN,
      .INIT_DATA_OUT,
      .WAIT,
      .INIT_WHICH_BYTE);




FETCH f(.clk(clk), .PC(addr), .enable(enable), .mem_data(mem_data), .mem_addr(mem_addr), .icode(icode), .ifun(ifun), .rA(rA), .rB(rB), .valC(valC), .valP(valP), .WAIT(WAIT));

initial addr = 32'b1000000; 

initial
 begin
    $dumpfile("test.vcd");
    $dumpvars(0,TB_MEM);
 end

initial #50 $finish;

initial enable = 1;

endmodule
